1. Field of the Invention
The present invention relates to a computer-implemented method of defect analysis for analyzing failure causes such as electrical properties on a semiconductor device on which presence/absence of defects can be checked at some point in a manufacturing process.
2. Description of the Background Art
As a background-art defect analysis method for analyzing failure causes such as electrical properties on a semiconductor device on which presence/absence of defects can be checked at some point in a manufacturing process, an analysis method is disclosed in Japanese Patent Application Laid Open Gazette No. 11-264797.
Disclosed in the above gazette is a defect analysis method paying its attention to new defects caused in a predetermined process step among a plurality of manufacturing process steps. The background-art defect analysis method will be discussed below in detail.
For specific discussion, devices are manufactured through six process steps A, B, C, D, E and F and the devices are subjected to a defect inspection by an inspection apparatus after each of the process steps A to F.
It is assumed, for example, that a process for manufacturing a DRAM consists of six process steps, i.e., the process step A of forming patterns of underlying oxide films, the process step B of forming transistors (for memory cell array, for controlling the memory cell array and the like), the process step C of forming capacitors (for memory cell), the process step D of forming (interlayer) insulating films, the process step E of forming metal wires (in the direction of row) and the process step F of forming metal wires (in the direction of column).
In the following discussion, the process step D is regarded as the predetermined process step to make an analysis.
First, new defects caused in the process step D are extracted. In this case, as shown in FIG. 17, there are a lot of defects 5, such as pattern defects, foreign matters, contaminant deposition and damages, which are detected on a wafer map 4 after the process step D. Among the defects 5 on the wafer map 4, defects caused only in the process step D are judged to be new defects 9, which are present on new regions other than coordinates of new defects 6 to 8 on wafer maps 1 to 3, which are already detected in the process steps A to C precedent to the process step D, and coordinates of defect neighborhood regions including error ranges 15.
Specifically, as shown in the graph of FIG. 18, the number of defects which is obtained by subtracting the number of new defects 6 to 8 detected in the process steps A to C and the number of defects on the same coordinates as the error ranges 15 from the total number of defects 5 on the wafer map 4 of the process step D corresponds to the number of new defects 9.
Next, after the process steps A to F are finished, a judgment result of pass/fail is obtained on respective integrated circuits formed on all the chips on a wafer with an electrical tester for judging pass/fail on an electrical operation. Further, the electrical tester generally performs a pass/fail test on the basis of a comprehensive result obtained through a plurality of partial electrical tests each for judging pass/fail on a specific electrical property.
Then, as shown in FIG. 19, a plurality of extracted chips on which presence/absence of the new defects 9 caused only in the process step D is judged and a plurality of chips on which pass/fail is judged as above are collated on a wafer map 20. As shown in FIG. 19, there are 52 new defects caused in the process step D, which are distributed in 45 chips. There are 78 faulty chips detected by the electrical tester and 57 good chips, totally 135 chips.
These 135 chips are classified by chips into four sorts, i.e., {circle around (1)} 48 good chips without defect, {circle around (2)} 42 faulty chips without defect, {circle around (3)} 9 good chips with defect and {circle around (4)} 36 faulty chips with defect, as shown in FIG. 20.
In this defect analysis method, even a chip with more than one defect is classified into the same category of xe2x80x9cwith defectxe2x80x9d as a chip with only one defect. Though there is another method in which a chip with more than one defect is weighted accordingly, in this defect analysis method, calculation proceeds without weighting. After this point, the number of defects is not involved in this analysis procedure and counting is made simply on the number of chips with defect. Therefore, since a chip with collective defects is regarded as a chip in the class {circle around (3)} or {circle around (4)}, classification considering little effect of collective defects can be performed.
Herein discussion will be made on the meaning of classification of the chips into four sorts. The classes {circle around (3)} and {circle around (4)}, which include the chips with defect, are affected by the process step D. In contrast to this, the classes {circle around (1)} and {circle around (2)} are unaffected by the process step D. Accordingly, the classes {circle around (1)} and {circle around (2)} have better yield than the classes {circle around (3)} and {circle around (4)}. The classes {circle around (1)} and {circle around (2)}, however, are affected by any one of the five process steps A, B, C, E or F. Therefore, if the classes {circle around (3)} and {circle around (4)} are unaffected by the process step D, it can be supposed that the classes {circle around (3)} and {circle around (3)} should have the same yield as the classes {circle around (1)} and {circle around (2)}.
The rate of failure RB1 (=1xe2x80x94the rate of good=1xe2x80x94yield) of the classes {circle around (1)} and {circle around (2)} is expressed as the following equation (1), wherein it is assumed that {circle around (1)} the number of good chips without defect is N1, {circle around (2)} the number of faulty chips without defect is N2, {circle around (3)} the number of good chips with defect is N3 and {circle around (4)} the number of faulty chips with defect is N4.                     RB1        =                              N2                          (                              N1                +                N2                            )                                =                      42                          (                              48                +                42                            )                                                          (        1        )            
Applying Eq. 1 to the classes {circle around (3)} and {circle around (4)}, the number NE of faulty chips which are affected by any one of the five process steps A, B, C, E or F other than the process step D is obtained as the following equation (2):
NE=(N3+N4)xc3x97RB1=(9+36)xc3x97RB1=21xe2x80x83xe2x80x83(2) 
Since the actual number of faulty chips in the classes {circle around (3)} and {circle around (4)} is the number of chips in the class {circle around (4)}, the number N0 of new faulty chips which are estimated to be failed only by the new defects caused in the process step D is obtained as the following equation (3):
N0=N4xe2x88x92NE=36xe2x88x9221=15xe2x80x83xe2x80x83(3) 
Next, the fatality rate RF of the new defects in the process step D is calculated. From the relation between the rate of failure RB1 in the classes {circle around (1)} and {circle around (2)} and the rate of failure RB3 in the classes {circle around (3)} and {circle around (4)}, i.e., RB3=N4/(N3+N4)=36/(9+36), the effect of the process step D is considered. Suppose that distribution of defects caused in the process step D is uniform in the areas {circle around (3)} and {circle around (4)}, the rate of good RG in the process step D is obtained as the following equation (4), according to the law of probability product, on the basis of the rate of good rg1 (=N1/(N1+N2)) in the classes {circle around (1)} and {circle around (2)} and the rate of good rg3 (=N3/(N3+N4)) in the classes {circle around (3)} and {circle around (4)}.                     RG        =                              rg3            rg1                    =          0.375                                    (        4        )            
Accordingly, the fatality rate RF of the new defects in the process step D is determined by the following equation (5):
RF=1xe2x88x92RG=0.625xe2x80x83xe2x80x83(5) 
This means that 62.5% out of the chips with new defect which are detected by the inspection apparatus are fatal. In this case, the inspection apparatus detects the defects which are not fatal as to 37.5% of the chips and this means that the inspection apparatus works with sufficiently high sensitivity. Thus, with fatality rate, the index of sensitivity of the inspection apparatus can be calculated.
Further, in this supposition, it is only necessary that the distribution of defects caused by the process step D should be uniform in the areas {circle around (3)} and {circle around (4)} and it is not necessary that the distribution should be uniform in 135 chips on the whole wafer.
Next, the number of faulty chips caused in the process step D is calculated. From the fact that 62.5% out of the detected chips with new defect are fatal, the number NB of process faulty chips can be obtained as the following equation (6):
NB=(N3+N4)xc3x97RF=28.1xe2x80x83xe2x80x83(6) 
FIG. 21 is a Venn diagram showing this analysis result. Out of 135 chips on the whole wafer, 57 chips are good and 78 chips are failure. Out of 78 faulty chips, the number NB of process faulty chips caused in the process step D is 28.1, and out of these chips, the number N0 of new faulty chips caused only in the process step D is 15. In other words, it is estimated that 13.1 (=28.1xe2x88x9215) chips should become failure in any one or more of the five steps A, B, C, E and F, having nothing to do with the process step D.
Accordingly, out of 78 faulty chips, 63 (=78xe2x88x9215) chips become failure in any one or more of the five steps A, B, C, E and F. Specifically, even if the failure caused by the process step D is completely eliminated and the number of faulty chips caused in the process step D is made 0 from 28.1, for example, there are still 63 faulty chips and the number of good chips increases only by 15. Thus, with the number N0 of new faulty chips in the process step D, the number of good chips which is estimated to increase if the failure in the process step D is completely eliminated can be quantitatively recognized.
In contrast to this, the number NB (=28.1) of process faulty chips on the basis of the fatality rate of the process step D indicates the number of chips to be still failure even if the yield of the five process steps A, B, C, E and F becomes 100%. In other words, the number NB of process faulty chips is a number quantitatively indicating the effect on the yield of only the process step D, and as the number becomes larger, adverse effect on the yield becomes larger.
Though the number of chips which is not integer is obtained by calculation in the above discussion, this number is obtained by calculation under the supposition that the distribution of defects should be uniform, and the like, and there is no problem if the number is used as the analysis result. Thus, the effect on the yield in single process step can be quantitatively calculated.
FIG. 22 is a flowchart showing the defect analysis method in the background art. Discussion will be made below on the procedure of the background-art defect analysis method, assuming that a predetermined process step is the process step D shown in FIGS. 17 and 18.
Referring to FIG. 22, the coordinates of new defects in the predetermined process step and the detection size are extracted by the inspection apparatus after the predetermined process step in the step S1, and judgment on pass/fail is performed by chips with the electrical tester after all the process steps are finished in the step S2. Then, in the step S3, presence/absence of new defects is judged by chips under a discriminating condition that all the detected new defects should be effective.
Next, in the step S4, as shown in FIG. 19, the new defects detected in the step S3 and the pass/fail judgment result obtained in the step S2 are collated on the wafer map and the chip classification data in which the chips are classified into four sorts as indicated by {circle around (1)} to {circle around (4)} of FIG. 20 is obtained on the basis of the presence/absence of the new defects and the pass/fail judgment.
After that, in the step S5, the rate of failure RB1 in the classes {circle around (1)} and {circle around (2)}, the number NE of faulty chips caused by any of the process steps other than the predetermined process step and the number N0 of new faulty chips which are judged failure only by the new defects caused in the predetermined process step are obtained, as shown in Eqs. (1) to (3). From this number N0 of new faulty chips, the number of faulty chips which would be reduced if the predetermined process step is improved can be quantitatively recognized.
Next, in the step S6, the rate of good RG on the basis of the rate of good rg3 in the classes {circle around (3)} and {circle around (4)} and the rate of good rg1 in the classes {circle around (1)} and {circle around (2)} and the fatality rate RF of the new defects caused by the predetermined process step on the basis of the rate of good RG are obtained, as shown in Eqs. (4) and (5). From this fatality rate RF, the sensitivity of the inspection apparatus which performs the defect inspection after the predetermined process step can be quantitatively recognized.
Finally, in the step S7, the number NB of process faulty chips caused in the predetermined process step is obtained on the basis of the fatality rate RF, as shown in Eq. (6). From this number NB of process faulty chips, the effect on the yield of device in the predetermined process step alone can be quantitatively recognized.
As discussed above, in the background-art defect analysis method, the defect analysis processing is performed on the basis of the chip classification data in which the chips are classified into four sorts, i.e., xe2x80x9c{circle around (1)} good chips without defect, {circle around (2)} faulty chips without defectxe2x80x9d, {circle around (3)} good chips with defect and {circle around (4)} faulty chips with defectxe2x80x9d.
If there is an extreme bias among the numbers of chips N1 to N4 in the classes {circle around (1)} to {circle around (4)} and any of the numbers of chips N1 to N4 is extremely small, however, there is good possibility that the analysis result should be largely changed by slight increase and decrease in the respective numbers of classified chips.
Thus, in the background-art defect analysis method, since the analysis result is largely changed by slight increase and decrease in the respective numbers of classified chips, there arises a problem that the reliability of the analysis result may become low.
It is an object of the present invention is to provide a defect analysis method or a method of verifying chip classification data, by which the reliability of the chip classification data and the analysis result can be enhanced.
The present invention is directed to a computer-implemented method of defect analysis for a device in which an integrated circuit is formed on each of a plurality of chips on a wafer through a plurality of process steps. According to the present invention, the defect analysis method includes the following steps (a) to (f). The step (a) is to detect defects after performing at least one of the plurality of process steps. The step (b) is to judge pass/fail of the integrated circuit of each of the plurality of chips after the plurality of process steps. The step (c) is to judge presence/absence of any of the defects which satisfies a predetermined discriminating condition on each of the plurality of chips in every the at least one process step. The step (d) is to obtain chip classification data in which the plurality of chips are classified into four sorts on the basis of combination of a judgment result of the step (b) and that of the step (c) in every the at least one process step. The step (e) is to calculate the random probability of failure which is a probability that faulty chips not less than the corresponding number of faulty chips with defect should be included in chips of the corresponding number of defective chips which are randomly extracted out of the plurality of chips on the basis of the chip classification data, and in the defect analysis method of the first aspect, the corresponding number of defective chips is equal to the number of chips which are judged to have a defect in the step (c), and the corresponding number of faulty chips with defect is equal to the number of chips which are judged to have a defect in the step (c) and judged to be failed in the step (b). The step (f) is to judge adoption/rejection of the chip classification data on the basis of the random probability of failure and performing a defect analysis processing on the basis of the chip classification data if adopted, to output an analysis result.
By adopting the chip classification data on the basis of the random probability of failure which is a probability that the same phenomenon occurs as in the case of extracting the chips xe2x80x9cwith defectxe2x80x9d even when the chips are randomly extracted, it is possible to enhance the reliability of the analysis result.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.